This invention relates to manufacturing of memory modules, and more particularly for processes for stacking memory chips.
The popularity of memory modules today is quite high. Many devices besides personal computers (PC's) use memory modules. Most PC's are shipped with sockets for memory modules so that the owners can later add additional modules, increasing the memory capacity of their PC's. High-volume production and competition have driven module costs down dramatically, benefiting the buyer.
Memory modules are made in many different sizes and capacities, with the old 30-pin modules replaced by 72-pin, 168-pin, and larger modules. The “pins” were originally pins or leads extending from the module's edge, but now most modules are leadless, having metal contact pads or fingers. The modules are small in size, some being about 5.25 inches long and 1.2 or 1.7-inches high.
The modules contain a small printed-circuit board (PCB) substrate, typically a multi-layer board with alternating laminated layers of fiberglass insulation and foil or metal interconnection layers. Surface mounted components are soldered onto one or both surfaces of the substrate. Dynamic-random-access memory (DRAM) integrated circuits (IC's) or chips are commonly packaged in inexpensive surface-mount packages such as small-outline J-leaded (SOJ) packages, plastic leaded chip carriers (PLCC), small-out-line packages (SOP) or thin small-outline packages (TSOP).
The number of DRAM chips used in a module depends on the capacity and data-width of the DRAM chips and the size of the memory module. For example, a memory module constructed from 64 Mega-bit×4-bit-output DRAM chips requires 16 of these 4-bit-wide DRAM chips to fill a 64-bit data bus. The module then has a capacity of 512 Megabytes (MB).
FIG. 1 is a schematic of a memory module with two banks of DRAM chips. DRAM chips 12–16 form a first bank, while DRAM chips 22–26 form a second bank. A total of 16 DRAM chips 12–16 are in the first bank, while another 16 DRAM chips 22–26 are in the second bank. When 64 Mega-bit×4 DRAM chips are used, each bank contains 512 MB.
Most signals are shared by all DRAM chips in both banks. For example, control signals such as RAS (row address strobe), CAS (column address strobe), WE (write-enable), clock, etc. and address lines are connected to all DRAM chips in both banks on the memory module. Data lines are each shared by one chip in each of the banks. Data lines D0–D3 are shared by DRAM chip 12 in the first bank and DRAM chip 22 in the second bank. Likewise, data lines D4–D7 are shared by DRAM chips 13, 23.
The banks are selected by chip-select signals. Only one chip select is activated at a time for the memory module. Chip select CS1 activates DRAM chips 12–16 in the first bank, while chip select CS0 selects DRAM chips 22–26 in the second bank. When the bank's chip select is not activated, the control signals are ignored by DRAM chips in the bank. The data lines are not driven by the non-selected bank of DRAM chips to prevent data conflicts.
FIG. 2 shows a prior-art double-bank memory module with stacked DRAM chips. While a 2-bank memory module can be constructed from non-stacked chips, twice as much surface area on the substrate would be needed. The memory module contains a substrate 10, with surface-mounted DRAM chips 22–26 mounted directly to the front surface or side of substrate 10, while more DRAM chips (not visible) are mounted to the back surface or side of substrate 10. Eight stacks of DRAM chips can be mounted on the front surface of substrate 10 for bits D0–31, while another eight stacks of chips can be mounted on the back surface for bits D32–63. Metal contact pads 20 are positioned along the connector edge of the module on both front and back surfaces. Metal contact pads 20 mate with pads on a module socket to electrically connect the module to a PC's motherboard. Holes and/or notches are usually used to ensure that the module is correctly positioned and securely seated in the socket.
Often the number of DRAM chips desired on a memory module is larger than the available substrate surface area. One method to mount more DRAM chips to a module is to stack DRAM chips on top of one another. For example, DRAM chip 12 can be mounted directly on top of DRAM chip 22. The leads or pins of upper DRAM chip 12 can be soldered to the leads or pins of lower DRAM chip 22.
Usually DRAM chips from separate banks are stacked together. The DRAM chips stacked together share the same data lines as well as control signals. DRAM chips 12–16 of the first bank are stacked on top of DRAM chips 22–26 of the second bank. When chips are mounted on both sides of substrate 10, two chips can be stacked together on the front surface and two chips can be stacked together on the back surface at each mounting location of the substrate. Each surface can have 8 mounting locations for DRAM chips, for a total of 16 mounting locations (only 5 locations are shown in the Fig.). With stacking, a total of 32 DRAM chips can be mounted to substrate 10.
FIG. 3 is an exploded view showing stacking of a pair of DRAM chips. Upper DRAM chip 12 of the first bank is mounted on the top of the stack, with lower DRAM chip 22 mounted below onto the module substrate. One side of pins is shown, but pins are usually on two or even on all four sides or edges of a DRAM IC package.
Between upper DRAM chip 12 and lower DRAM chip 22 is thin PCB 30. Thin PCB 30 is a thin circuit board that can be made from fiberglass with printed metal layers on its two major surfaces. Thin PCB 30 has bonding pads 40 on its upper surface that are arranged for making contact with the pins S1–S7 from upper DRAM chip 12. The pins from upper DRAM chip 12 are soldered to these bonding pads 40 on the upper surface of thin PCB 30 during manufacturing.
The bottom surface of thin PCB 30 also has leads C1–C7 that are aligned to make contact with the tops of the pins S1–S7 of lower DRAM chip 22. These leads C1–C7 of thin PCB 30 are soldered to the pins S1–S7 of lower DRAM chip 22. Thus thin PCB 30 has bonding pads on the top surface that are soldered to pins of upper DRAM chip 12, and has leads that are soldered to pins of lower DRAM chip 22.
Each of the leads is connected to an upper bonding pad either directly above or through a drilled via or a metalized connection through the substrate of thin PCB 30. Thus thin PCB 30 electrically connects pins from lower DRAM chip 22 to the pins of upper DRAM chip 12 that are directly above.
All of the address, data, RAS, CAS, clock, power, ground, and most other signals are shared among the two stacked DRAM chips 12, 22 in this way by directly connecting corresponding pins S1–S7 in upper and lower DRAM chips 12, 22. For example, pin 1 (signal S1) of upper DRAM chip 12 caries signal S1 and connects through the first of bonding pads 40 on the top surface of thin PCB 30 to lead C1 which is soldered to pin 1 (also signal S1) of lower DRAM chip 22.
While most pins of lower DRAM chip 22 are connected with the pins directly above of upper DRAM chip 12, there are some exceptions. The chip-select pins are disconnected and re-routed by thin PCB 30 so that the stacked DRAM chips receive different chip-select signals. This allows one of the DRAM chips 12, 22 to be selected and the other de-selected.
For example, chip select CS0 connects to lower DRAM chip 22 through pin 3. Chip select CS0 controls the second DRAM bank that includes lower DRAM chip 22. The connection from CS0 to thin PCB 30 is broken by the removal or lack of lead C3 of thin PCB 30. Without the C3 lead, no connection is made between pin 3 of lower DRAM chip 22 and thin PCB 30.
DRAM chips often include unused pins known as no-connect (NC) pins. These pins do not connect to circuitry inside the DRAM chip, but are still present as physical pins or leads on the chip package. In this example, DRAM chips 12, 22 have pin 5 as a NC pin.
Another chip-select CS1 signal from the memory module substrate is connected to pin 5 of lower DRAM chip 22. Rather than leave an isolated bonding pad on the substrate of the memory module under pin 5, this bonding pad is connected by metal traces on the memory module substrate to the CS1 signal line. Since pin 5 is a NC pin, lower DRAM chip 22 ignores this CS1 signal.
However, pin 5 of lower DRAM chip 22 is soldered to lead C5 of thin PCB 30. Wiring trace 32 on thin PCB 30 electrically connects lead C5 to another one of bonding pads 40, the bonding pad with the missing C3 lead. This bonding pad is soldered to pin 3 of upper DRAM chip 12. Thus the CS1 signal from the memory-module substrate is routed up through the no-connect (NC) pin 5 of lower DRAM chip 22 to lead C5 of thin PCB 30. Then wiring trace 32 moves this CS1 signal from C5 to the bonding pad for the missing C3 lead. From this bonding pad for C3, the CS1 signal is carried to pin 3 of upper DRAM chip 12. Pin 3 of DRAM chips 12, 22 is the chip-select input.
Thin PCB 30 allows lower DRAM chip 22 to receive CS0 at its pin-3 chip-select input, while routing CS1 from an unused (NC) pin 5 of lower DRAM chip 22 to the pin-3 chip-select input of upper DRAM chip 12. Other pins may be the NC pin although pin 5 is chosen in the above illustration, for example, the adjacent pin-4 could have been the NC pin.
FIG. 4 shows prior-art DRAM stacked chips using a bent lead-frame. Rather than use thin PCB 30 of FIG. 3, a lead-frame may be used to connect the stacked chips. A bend-ing machine may bend downward the ends of each of the leads on lead-frame 38. Bending the leads downward produces a 90-degree bend as shown. The bent downward portion of each lead is soldered to the tops of lower-chip pins 36, while upper-chip pins 34 from upper DRAM chip 12 are soldered to the non-bent portions of each lead of lead-frame 38. Thus pins (leads) of upper DRAM chip 12 are connected to pins (leads) of lower DRAM chip 22 by bent leads of lead-frame 38.
Leads for chip-select (CS) and no-connect (NC) pins of the DRAM chip can be specially designed for jumper use. A lead for a no-connect pin can be cut off and can be indirectly connected to the lead-frame by the lead for the chip-select pin through a jumper bridge inside of the frame opening. The lead for the no-connect pin is bent downward but from an opposite direction of leads for standard pins, whereas the lead for the chip-select pin stays non-bent. Thus, another chip-select signal CS1 (as in FIG. 3) from the memory-module substrate is routed through the no-connect pin of lower chip 22 to the chip-select pin of upper chip 12.
While useful, such bent-leads of lead-frame 38 are difficult to work with for manufacturer. Bending of the tiny leads on lead-frame 38 is difficult. Lead ends can break off during the bending process, or the angle of bending might not be consistently 90 degrees, causing registration or alignment problems with the tops of lower-chip pins 36 of lower DRAM chip 22. Maintaining co-planarity of all the many bent leads is very difficult, and standard solder printing (especially controlling solder volume) is difficult when leads are not co-planar. Bent leads thus might not be properly soldered to lower-chip pins 36 as a result. Bending some leads but not others on lead-frame 38 makes the process challenging. Bending leads for no-connect pins in an opposite direction produces additional process complexity.
What is desired is an improved process for making stacked memory chips that does not require bending of the leads of a lead-frame. A stacking process using unbent leads in a flat lead-frame is desired.